System-aware PCI Express® retimers support diverse interconnect
topologies, plug-and-play interoperation at speeds up to 32 GT/s
SANTA CLARA, Calif.–(BUSINESS WIRE)–lt;a href=”https://twitter.com/hashtag/DataCenters?src=hash” target=”_blank”gt;#DataCenterslt;/agt;–Astera
Labs Inc., a maker of purpose-built connectivity solutions for
intelligent systems, today announced the industry’s first Peripheral
Component Interconnect PCI Express® (PCIe®) 5.0 retimer technology,
specifically designed to remove performance bottlenecks and signal
integrity challenges in next-generation servers. This breakthrough,
system-aware technology makes it possible for hyperscale data center
system designers to create a robust server connectivity backbone tying
together processors, workload accelerators and storage nodes over
diverse system topologies at speeds up to 32 gigatransfers per second
Servers have been operating with PCIe 3.0 technology for many years.
With PCIe 4.0 processors entering the market and the PCIe
5.0 specification now released, system designers are rapidly gearing
up for the increased bandwidth enabled by these new standards. “At 16
and 32 GT/s, retimers play a crucial role to achieving diverse system
topologies and accelerating the shift to blazing-fast speeds,” said Al
Yanes, PCI special interest group (SIG) chairman and president.
“Heterogeneous computing and workload-optimized platforms are redefining
the connectivity backbone in the next generation of servers. Specialized
semiconductors will help enable this high-speed connectivity backbone
and accelerate technology adoption,” said Jitendra Mohan, CEO at Astera
Labs. “Our system-aware retimers are designed to empower system
designers to easily upgrade from PCIe 4.0 to PCIe 5.0 technology and
achieve plug-and-play interoperation without compromising interconnect
topologies even at 32 GT/s speeds.”
“The explosion of data and new compute-intensive workloads, like
artificial intelligence and machine learning, is driving the need for
faster and lower-latency interconnects in data-centric systems,” said
Amber Huffman, Intel fellow, Data Center Group. “Intel is embracing and
leading the transition with its support for the new PCIe 5.0
specification and the announcement of Compute Express Link (CXL)
technology. We are excited that Astera Labs has entered the ecosystem to
develop purpose-built connectivity solutions to enable seamless adoption
of these technologies.”
Find out more about artificial intelligence and machine learning compute
and connectivity challenges in modern servers:
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Astera Labs is working with customers and partners now to build PCIe
retimers based on its system-aware technology. Get specifications and
more information at firstname.lastname@example.org.
About Astera Labs
Astera Labs Inc., a fabless semiconductor company headquartered in the
heart of California’s Silicon Valley, develops purpose-built
connectivity solutions for data-centric systems. The company’s product
portfolio includes system-aware semiconductor integrated circuits,
boards and services to enable robust PCIe connectivity. Partnering with
leading processor vendors, cloud service providers, seasoned investors
and world-class manufacturing companies, Astera Labs is helping
customers remove performance bottlenecks in compute-intensive workloads.
For more information about Astera Labs, see www.asteralabs.com.
PCI-SIG is the consortium that owns and manages PCI specifications as
open industry standards. The organization defines industry-standard
input/output specifications consistent with the needs of its members.
Currently, the PCI-SIG comprises over 700 industry-leading member
companies. To join the PCI-SIG or for a list of the board of directors,
Astera Labs and the Astera Labs logo are trademarks of Astera Labs Inc.
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